"The collaboration with Cadence is integral to the success of our customers delivering advanced analog/mixed-signal designs," said Tom Quan, deputy director of design methodology and service marketing at TSMC. "The TSMC AMS Reference Flow for 28 nanometer represents the industry's most complete methodology for creating, verifying and producing silicon that takes advantage of the latest process technology. We look forward to continuing our work with Cadence and the entire TSMC Open Innovation Platform ecosystem to ensure that our technologies keep pace with emerging design challenges and maximize our customers' investment in design infrastructure."
The reference flow enhancements deliver significant assistance to design teams tasked with achieving efficient and cost-effective Silicon Realization, a key pillar of the Cadence EDA360 strategy.
Cadence mixed-signal technologies provide extremely comprehensive support for TSMC's new 28-nanometer reference flow, addressing the steps required to get a design into silicon. The collaboration between Cadence and TSMC directly addresses the increasing complexity and integration in analog and mixed-signal functionality in the silicon designs used in wireless, networking, consumer and other applications.
"With the increasing complexity of wireless, networking, consumer and CPU designs, the analog and mixed-signal IP can represent more than 50 percent of a chip design," said Sandeep Mehndiratta, group director of product management at Cadence. "Cadence's support of TSMC AMS Reference Flow 1.0 optimized for TSMC silicon technology delivers a comprehensive design, verification and implementation solution to our customers for realizing highest quality advanced mixed-signal designs on 28 nanometers."
The TSMC reference flow incorporates the broad suite of Cadence technology offerings from the Virtuoso platform, delivering extensive coverage for design, verification and implementation of AMS IP on 28 nanometers. Based on proven methods for advanced 28-nanometer designs, Cadence technology, in collaboration with TSMC, enables schematic design, AMS verification, RF and transient noise analysis, yield sensitivity analysis, constraints-driven layout, analog placement and routing, physical verification, DFM-aware parasitic extraction, IR drop and electromigration analysis.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at
www.cadence.com.
Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc., in the USA and other countries. All other marks and names are the property of their respective owners
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