Renesas specifically developed their LogicBench prototyping system to begin hardware-software integration and debugging well before silicon is available. However, use of FPGA-based prototyping methods can limit the ability to locally detect and debug hardware design errors. To address this problem, Renesas required technology that enabled assertions that are specified in any format, including standard assertion languages and libraries, to be compiled directly into LogicBench, providing observability comparable to software simulation. As the industry's leading solution for assertion-based verification, the 0-In Assertion Synthesis tool was chosen and extended to support the Renesas' verification flow.
"We needed an assertion-based verification method that includes simulation and formal verification to strengthen our verification solution based on LogicBench," stated Mr. Osamu Tada, department manager of System Level Design and Verification Technology, Design Technology Division, LSI Product Technology Unit of Renesas Technology Corp. "We selected Mentor's 0-In Assertion Synthesis technology because it provides the best solution for our target."
Assertion-based verification provides the observability and controllability required to verify today's complex system-on-chip (SoC) designs. Applying the 0-In Assertion Synthesis tool simplifies the specification of assertions by automatically extracting design data (for example: clocks, resets and variable names) from register-transfer level (RTL) code. This unique design inference capability allows assertions to automatically adapt to design changes and significantly reduces the maintenance required as the design evolves. Compared to other methods, the 0-In Assertion Synthesis technology significantly simplifies the task of finding and determining the cause of bugs. The 0-In Assertion Synthesis supports all standard assertion formats including Accellera's Property Specification Language (PSL), SystemVerilog assertions (SVA), the Open Verification Library (OVL), the CheckerWare(R) tool, and the 0-In assertion library. The assertions generated by the 0-In Assertion Synthesis system can be used with standard simulators, formal engines, emulators or hardware prototyping systems.
"Leading design teams require a full-range of assertion checkers and protocol monitors that are interoperable with leading verification tools. In order to take full advantage of the capabilities on LogicBench, Renesas needed a unique capability for gathering and reporting error detection and coverage information," stated Steven D. White, general manager of Mentor Graphics 0-In Verification Business Unit. "Our assertion synthesis technology provided the right answer."
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $700 million and employs approximately 3,850 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/.
Mentor Graphics, 0-In and CheckerWare are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
Contact:
Mentor Graphics Larry Toda, 503-685-1664 Email Contact or Ry Schwark, 503-685-1660 Email Contact
