Lattice Accelerates FPGA Design with New Lattice Radiant 2.0 Design Software

Latest Version Supports New Lattice CrossLink-NX FPGAs

HILLSBORO, Ore. — (BUSINESS WIRE) — December 10, 2019Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced the availability of the latest version of its popular software design tool for FPGAs, Lattice Radiant™ 2.0. In addition to adding support for higher density devices like the new CrossLink-NX™ FPGA family, the updated design tool also offers new features that make it faster and easier than ever to develop Lattice FPGA-based designs.

When system developers evaluate hardware platforms, the actual hardware is only a part of their selection criteria. They also evaluate the design software used to configure the hardware for its ease-of-use and supported features, as these features can have a significant impact on overall system development time and cost.

Roger Do, Senior Product Line Manager, Software at Lattice said, “Lattice Radiant 2.0 design software gives developers an easy-to-follow user experience; the tool leads them through the design flow from design creation, to importing IP, to implementation, to bitstream generation, to downloading the bitstream onto an FPGA. Developers with little to no experience working with FPGAs should be able to quickly leverage the automated features of Lattice Radiant. For experienced FPGA developers, Lattice Radiant 2.0 allows for more granular control over FPGA settings if specific optimizations are required.”

New feature upgrades available in Radiant 2.0 include:

  • An on-chip debugging tool that allows users to conduct bug fixes in real time. The debugging feature lets developers insert virtual switches or LEDs in their code to confirm viability. The tool also lets users change hard IP block settings to test different operating modes.
  • Improved timing analysis provides more accurate trace and route planning and clock timing to avoid design congestion and thermal issues.
  • The engineering change order (ECO) editor lets developers make incremental changes to a completed design without having to recompile the entire FPGA database.
  • The Simultaneous Switching Output (SSO) calculator analyzes the signal integrity of individual pins to ensure their performance isn’t adversely affected by their proximity to another pin.

For more information, please visit www.latticesemi.com/LatticeRadiant.

About Lattice Semiconductor

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.

For more information about Lattice, please visit www.latticesemi.com. You can also follow us via LinkedIn, Twitter, Facebook, YouTube, WeChat, Weibo or Youku.

Lattice Semiconductor Corporation, Lattice Semiconductor (& design) and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. The use of the word “partner” does not imply a legal partnership between Lattice and any other entity.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.



Contact:

MEDIA CONTACTS:
Bob Nelson
Lattice Semiconductor
408-826-6339
Bob.Nelson@latticesemi.com

INVESTOR CONTACT:
Rick Muscha
Lattice Semiconductor
408-826-6000
Rick.Muscha@latticesemi.com

Featured Video
Jobs
Senior SOC Design Engineer for Nvidia at Santa Clara, California
Advanced Mechanical Engineer for General Dynamics Mission Systems at Marion, Virginia
Senior CAD Engineer for Nvidia at Santa Clara, California
RF Design Engineer for Blockwork IT at San Francisco, California
Hardware System Engineer for Google at Mountain View, California
Senior DPU System Application Engineer for Nvidia at Santa Clara, California
Upcoming Events
3D & Systems Summit - Heterogeneous Systems for the Intelligently Connected Era at Hilton Dresden Hotel An der Frauenkirche 5, 01067 Dresden Germany - Jun 12 - 14, 2024
2024 IEEE Symposium on VLSI Technology & Circuits at HILTON HAWAIIAN VILLAGE HONOLULU HI - Jun 16 - 20, 2024
Design Automation Conference (DAC) 2024 at Moscone West, San Francisco CA - Jun 23 - 27, 2024
SemiconWest - 2024 at Moscone Center San Francisco CA - Jul 9 - 11, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise