ZTE Selects Intel's eASIC Devices for 5G Wireless Deployment

May 05, 2019 -- What’s New: Intel today announced that  ZTE*, a multinational telecommunications equipment and systems company, selected Intel® eASIC™ devices for its 5G wireless products. ZTE selected Intel eASIC devices to meet the critical cost and power requirements demanded by large-scale 5G deployments.

“Intel’s alliance with ZTE marks a major milestone in Intel eASIC devices’ 5G penetration. 5G speeds will enable new classes of applications, resulting in an exponential increase in data volume. Our customers need solutions that allow them to design optimal systems they can take to market quickly. Intel’s structured and standard ASICs enable ZTE to achieve critical cost goals and cement their position in the exploding 5G market.”

–Dan McNamara, Intel senior vice president and general manager of the Programmable Solutions Group

Why It’s Important: As 5G rollout moves from the trial phase to initial deployment, carriers need flexible solutions based on field programmable gate arrays (FPGAs). FPGAs provide hardware programmability to meet both prototyping and initial production requirements. As the 5G rollout transitions to high-volume production, FPGAs transition to ASICs to meet cost and power targets associated with high-volume shipments. Intel’s recent acquisition of eASIC enables a smooth transition from FPGA-based designs to structured ASICs.

ZTE used FPGAs for rapid prototyping and early production. The company needed to quickly transition to a lower unit cost and reduced-power solution for high-volume deployment.

“Intel eASIC devices provide good power and cost benefits for our 5G wireless products and were essential to make a fast transition to meet our low cost and power requirements,” said Duan Xiang Yang, vice president and general manager of Wireless System Architect at ZTE.

What It Does: A structured ASIC is an intermediary technology between FPGAs and standard-cell ASICs that provides unit-cost reduction and improved power efficiency. Structured ASICs offer benefits like those offered by standard-cell ASICs, but with faster development time. Intel eASIC devices are structured ASICs that provide a smooth design transition from any FPGA. They reduce unit cost and power consumption compared to FPGAs. These two benefits are especially important for high volume-markets, such as 5G radio.

What It Delivers: ZTE was able to meet time-to-market requirements using FPGAs for its 5G design. The smooth transition to an eASIC structured ASIC device reduces the design’s bill of materials (BOM) cost and power consumption, which is required for high-volume production. The combination of FPGAs and Intel eASIC structured ASICs allows customers to meet diverse time-to-market, flexibility, performance, low-power and unit-cost requirements.

What the Future Holds: The combination of Intel FPGAs, Intel eASIC devices and Embedded Multi-die Interconnect Bridge (EMIB) technology will enable a new device class with flexibility, lower unit cost and power efficiency, all in a single package.

About Intel

Intel (NASDAQ: INTC), a leader in the semiconductor industry, is shaping the data-centric future with computing and communications technology that is the foundation of the world’s innovations. The company’s engineering expertise is helping address the world’s greatest challenges as well as helping secure, power and connect billions of devices and the infrastructure of the smart, connected world – from the cloud to the network to the edge and everything in between. Find more information about Intel at  newsroom.intel.com and  intel.com.

Intel and the Intel logo are trademarks of Intel Corporation in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Featured Video
Editorial
More Editorial  
Jobs
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Upcoming Events
MEMS & Sensors Executive Congress (MSEC 2024) at Château-Bromont Hotel in Bromont Quebec Canada - Oct 7 - 9, 2024
PCB West 2024 at Santa Clara Convention Center Santa Clara CA - Oct 8 - 11, 2024
DVcon Europe 2024 at Holiday Inn Munich City Center, Munich Germany - Oct 15 - 16, 2024
International Test Conference (ITC) at United States - Nov 3 - 8, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise