What is Expression Coverability Analysis?
Measurements of statement and branch coverage are no longer considered sufficient for the
verification of HDL design representations. Because code coverage is very sensitive to RTL
writing style, the same functionality written in different ways can give different coverage results
depending on the style in which the code is written.
As a consequence, achieving even 100% statement and branch coverage does not ensure that
a design has been sufficiently exercised.
In order to improve confidence in coverage measurement, best practice now demands the use of
coverage for expressions in conditional statements, which means performing coverage analysis
at a greater level of detail.
Using technology that has been proved by aerospace industry experts to be equivalent to
Modified Condition/Decision Coverage (MC/DC), mandatory in safety-related applications,
TransEDA’s established Focused Expression Coverage (FEC) metric delivers this ultimate level
of accuracy in coverage measurement.
To promote easy and effective use of FEC, TransEDA introduces the unique Expression
Coverability Analysis facility as another breakthrough in coverage and formal technologies
integration.
Expression Coverability Analysis provides automatic in-depth analysis of conditional
expressions for designs written in Verilog, VHDL and mixed languages and, in doing so, guides
the user on the quickest route to full condition coverage.
Automatically and transparently using the power of an embedded formal engine, uncoverable
expression terms, and coverable terms that have not been exercised, are quickly identified. After
confirmation, uncoverable expression terms are reported and eliminated from the overall
coverage calculation.
Diagnostic information, including VCD files, is generated for currently uncovered, but testable
sub-expressions.
Quick isolation of unreachable expression terms allows engineers to achieve faster convergence
to full Focused Expression Coverage, reaching unparalleled accuracy in coverage
measurement.
Running from the command line or through a Graphical User Interface, and capable of being
easily and smoothly integrated into any design flow, Expression Coverability Analysis delivers
greater confidence in the completeness of the design verification process.
Availability
Design Coverability Analysis – including Branch and Expression Coverability Analysis – is available now as an option to VN-Cover on platforms running Solaris or Linux operating systems. For more information, a demonstration or an evaluation copy, contact your local representative or visit www.transeda.com.
TransEDA will demonstrate this new key capability at DATE (Design Automation and Test in Europe) that will take place in Munich from the 8 th to the 11 th of March 2005.
About TransEDA
TransEDA is a leading provider of coverage and ready-to-use verification solutions for electronic designs. The company has over twelve years operating experience in the EDA market.
TransEDA provides advanced verification and verification closure measurement solutions including code coverage with coverability analysis capability, specification coverage and impact analysis, configurable HDL rule checking with automatic formal checks, static assertion verification, automatic bus protocol checking, verification IP with bus-based system-level test automation, test suite optimization and transistor-level functional abstraction.
TransEDA is part of the Valiosys Group and has offices in North America, Europe and Japan, plus local representatives in China, India, Korea, Singapore and Taiwan. For more information, visit www.transeda.com.
Contacts
TransEDA - Sophie Gosselin, +33 (0)153 38 46 00,
Email Contact
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Technology Ltd. All other trademarks are the property of their respective owners.
