Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design

GUC performs complex SoC verification tests up to 795X faster

SAN JOSE, Calif. — (BUSINESS WIRE) — August 13, 2018 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Global Unichip Corporation (GUC) has adopted the Cadence® Palladium® Z1 Enterprise Emulation Platform to accelerate system-on-chip (SoC) design and drive innovation in the semiconductor industry. By combining the Palladium Z1 emulation platform with Cadence Xcelium Parallel Logic Simulation, GUC engineers were able to apply more complex SoC verification test scenarios with full debug visibility, accelerating verification by up to 795 times.

For more information on the Palladium Z1 Enterprise Emulation Platform, please visit www.cadence.com/go/palladiumz1guc.

The Palladium Z1 emulation platform allowed GUC to improve system-on-silicon verification and optimize hardware and software integration earlier in the verification process, ensuring high reliability. The compile capabilities included with the Palladium Z1 emulation platform also enabled GUC to achieve more predictable turnaround times for full-chip emulation model builds. This helped GUC engineers to debug quickly and explore design changes 20X faster, which was not feasible with other design methodologies.

In addition to using the Palladium Z1 emulation platform and Xcelium Parallel Logic Simulation, GUC also used other solutions in the Cadence Verification Suite including Verification IP (VIP) and the JasperGold® Formal Verification Platform. The broader Cadence Verification Suite provided GUC with automation, debug, tracking, management and measurement of verification tasks across verification flows and engines, which improved productivity and team collaboration. The Palladium Z1 emulation platform enabled congruency with the adjacent verification suite engines, allowing GUC to significantly optimize overall verification productivity, which ultimately led to improved product quality.

“A high-performance ASIC verification solution is vital for driving our product innovations and business, and we need to continually strive to improve our overall product quality,” said Dr. Ken Chen, president at Global Unichip Corporation. “After comparing alternative solutions in the market, we selected Cadence’s Palladium Z1 Enterprise Emulation Platform for its effectiveness in ASIC verification productivity and use-model versatility. Adopting the Palladium Z1 emulation platform in conjunction with Xcelium Parallel Logic Simulation and the broader Cadence Verification Suite has enabled us to deliver flexible ASIC services that elevate our visionary IC customers to the next level of leadership in their respective markets.”

The Palladium Z1 Enterprise Emulation Platform is part of the Cadence Verification Suite. It supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class JasperGold, Xcelium, Palladium Z1 and Protium S1 core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.



Contact:

Cadence Newsroom
408-944-7039
Email Contact

Featured Video
Jobs
Senior DPU System Application Engineer for Nvidia at Santa Clara, California
Senior Hardware Engineer IV – CA for Ampex Data Systems Corporation at Hayward, California
Hardware Engineer for PTEC Solutions at Fremont, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Post Silicon Hardware Engineer for Nvidia at Santa Clara, California
Upcoming Events
SemiconWest - 2024 at Moscone Center San Francisco CA - Jul 9 - 11, 2024
Flash Memory 2024 Conference & Expo FMS2024 at Santa Clara Convention Center Santa Clara CA - Aug 6 - 8, 2024
SEMICON Taiwan 2024 at Taipei Nangang Exhibition Center Taipei Taiwan - Sep 4 - 6, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise