Twenty fifth Annual IEEE Electronic Design Process Symposium

Twenty fifth Annual Electronic Design Process Symposium

September 13-14, 2018

Semi,  673 Milpitas Blvd, Milpitas, CA 95035

May 24, 2018 -- This year marks a milestone in the EDPS’s history as it turns 25.  We have come a long way since the early days of EDPS in Monterey.  In 1992, designs were beginning to truly explode rapidly moving into “very large scale integration” with companies racing to meet/beat the NTRS.  The words low-power and SoC design flows were but a whisper.  SIA was bringing out its first edition of National Technology Roadmap for Semiconductors, which subsequently transformed into ITRS, and now the Heterogeneous Integration Roadmap & International Roadmap for Devices & Systems. As these roadmaps project semiconductor industry evolution, EDPS strives to be the leading forum for advanced chip and systems development and CAD methodologies currently in practice within the industry.

As we approach the end of Moore’s law scaling, innovative packaging techniques are becoming increasingly important as package, board and other system components drive significant cost reduction. Innovative and smart manufacturing methodologies and flows are also becoming increasingly important. Since algorithmic development is changing rapidly, smart manufacturing enabling reduced NRE and faster time to market is critical.

Key changes in designs and design methodologies continue to be an EDPS focus; the leading industry members will be talking and sharing their challenges and solutions in this vibrant symposium. It’s the closest thing to real conversation about real design. EDPS 2018 sessions are based on the following themes

  • Cyber Systems Design with emphasis on security
  • Machine Learning in System Design and EDA
  • Smart Manufacturing – Increased cooperation between design and manufacturing, Advanced Packaging, IoT, Machine Learning, Cloud manufacturing, Supply Chain Safety
  • Innovative Designs and Design Techniques (incl. validation and debug)
  • System reliability with special focus on ADAS and 5G

 

Please contact Shishpal Rawat ( Email Contact) to submit abstract and discuss areas of mutual interest.  All presentations slides must be made available in final form by Aug 15, 2018.

Complete presentations from 2017 EDPS and previous years are available at:

http://edpsieee.ieeesiliconvalley.org/EDP2017/edps_program.php



Read the complete story ...
Featured Video
Jobs
Senior DPU System Application Engineer for Nvidia at Santa Clara, California
Senior CAD Engineer for Nvidia at Santa Clara, California
Senior Post Silicon Hardware Engineer for Nvidia at Santa Clara, California
Advanced Mechanical Engineer for General Dynamics Mission Systems at Marion, Virginia
Hardware Engineer for PTEC Solutions at Fremont, California
Senior SOC Design Engineer for Nvidia at Santa Clara, California
Upcoming Events
3D & Systems Summit - Heterogeneous Systems for the Intelligently Connected Era at Hilton Dresden Hotel An der Frauenkirche 5, 01067 Dresden Germany - Jun 12 - 14, 2024
2024 IEEE Symposium on VLSI Technology & Circuits at HILTON HAWAIIAN VILLAGE HONOLULU HI - Jun 16 - 20, 2024
Design Automation Conference (DAC) 2024 at Moscone West, San Francisco CA - Jun 23 - 27, 2024
SemiconWest - 2024 at Moscone Center San Francisco CA - Jul 9 - 11, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise