LIVE WEBINAR: HOW TO GET AN SOC POWER CONSUMPTION UNDER 0.5 µA IN SLEEP MODE

Grenoble, France - May 15, 2017 - Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC. For such applications, the design of the “Always-On power domain" is pivotal.

To meet customer expectations, ensuring a current consumption of the Always-On power domain - incl. blocks in retention mode - not higher than 500 nA is pivotal.

After the success of our webinar presenting the recipe for a low-power SoC, our chef is back with a successful and proven recipe to ensure the lowest power consumption in sleep mode(s).

This webinar focus on the power consumption optimization of the Always-on domain based on a concrete example.

By attending this webinar, architects and designers will analyze 5 power architectures through a figure of merit, to select the most appropriate architecture with the relevant silicon IPs to reach the targeted power consumption while ensuring:

  • the smallest silicon area
  • the lowest BoM cost

Register to this live webinar

You will be able to select your session:

  • in Mandarin, on May 18
  • in English
    • on May 23 for US Time zone
    • on June 1 for EU Time zone

If you want to watch the record of our previous webinar “The proven recipe for a low-power SoC”, you can ask an access to  MyDolphin.

For more information, contact  Email Contact, Marketing Manager

Featured Video
Latest Blog Posts
Vijay ChobisaSiemens EDA
by Vijay Chobisa
The Rise of Custom Acceleration
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Nomination Deadline for Phil Kaufman Award and Hall of Fame: June 30
Jobs
Senior DPU System Application Engineer for Nvidia at Santa Clara, California
Senior Post Silicon Hardware Engineer for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Hardware Engineer for PTEC Solutions at Fremont, California
Upcoming Events
Design Automation Conference (DAC) 2024 at Moscone West, San Francisco CA - Jun 23 - 27, 2024
SemiconWest - 2024 at Moscone Center San Francisco CA - Jul 9 - 11, 2024
Flash Memory 2024 Conference & Expo FMS2024 at Santa Clara Convention Center Santa Clara CA - Aug 6 - 8, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise