June 3-5, 2013, Austin Convention Center, Booth #2441

AUSTIN, Texas — (BUSINESS WIRE) — June 3, 2013 — True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries announced today the introduction of a new high performance DDR 4/3 PHY with state-of-the-art tuning and training, and remarkable physical flexibility to adapt to each customer’s die floorplan and package. The DDR 4/3 PHY has been developed using the powerful custom design automation tools that have made TCI’s line of high performance PLLs and DLLs a staple in the semiconductor industry for over 15 years. The availability of this revolutionary PHY means customers can now license a hard PHY with significant performance and features without all the implementation and timing closure hassles that are common with current DDR offerings.

The DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read data eye and gate timing are also continuously adjusted. Automatic training is included for multi-cycle read gate timing and write leveling, write data eye timing, and internal and external (on DRAM) Vref setting.

The PHY employs a localized, clock deskewed PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.

Remarkable physical flexibility allows the PHY to adapt to each customer’s die floorplan and package constraints, and is delivered and verified as a single hard macro for easy timing closure with no assembly required. The PHY is also DFI 3.1 compliant, and when combined with a suitable DDR 4/3 memory controller, a complete and fully-automatic DDR 4/3 system is realized.

“TCI has been providing high-performance PLL and DLL IP for a range of DDR applications since the early days of DDR. In working closely with our customers, it became clear to us that DDR is really a timing problem, one that requires a deep understanding of analog timing circuits, parallel interfaces and signal integrity,” remarked Stephen Maneatis, True Circuits’ CEO. “After seeing so many customers struggle with the challenges of higher speeds, integration complexity and timing closure, we decided to apply our over 15 years of experience in high performance analog timing IP, and design an entirely new DDR 4/3 PHY that addresses these challenges in a broad and comprehensive way. The result of this effort is a hard PHY that adjusts timing automatically to optimize performance, and is also easy to integrate and test. Customers have always been able to count on True Circuits timing IP for functionality, performance and quality, and they should expect nothing less from our new DDR 4/3 PHY IP.”

Availability and Licensing

The True Circuits DDR 4/3 PHY is initially available for customer delivery in TSMC’s 28nm HPM process. The PHY will be available in additional TSMC and GlobalFoundries processes in the very near future. Interested customers can obtain more product information on the web at www.truecircuits.com/ddr_phy.html or by contacting True Circuits at Email Contact.

About True Circuits Attendance at DAC

At the Design Automation Conference (DAC), True Circuits will feature its complete line of high performance and general purpose timing IP, as well as its revolutionary new DDR 4/3 PHY IP. Brian Gardner, True Circuits' V.P. of Business Development, will also make presentations about True Circuits and our new DDR PHY IP in the ChipEstimate.com booth #2446 and the TSMC OIP booth #1746 each day of the conference.

About True Circuits PLLs and DLLs

True Circuits offers a complete family of standardized and silicon-proven general purpose, clock generator, deskew, and spread spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks.