Date: Thursday, Feb 16, 2012
(Europe) Time: 3:00 PM - 4:00 PM CET
(US) Time: 11:00am – 12:00pm PST
To register, please visit aldec.com/events.
When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization. Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code.
Agenda:
- Introduction
- Emulation Debugging Concepts
- 100% Visibility during Dynamic Debugging
- Live Demonstration
- Q & A
